SPICE simulation convergence with suggestions (Innoveda)

Last browsed items

Users' reviews

Your contribution

In order to post your reviews, to rank a review or to send comments to the mailing-list, you need to log in.
If you have not yet created your account, please register.
In case of error or omission, please send us your feedback.

Large circuits and/or high gain circuits can cause SPICE to fail in convergence. The user is usually left with a cryptic message. This tech tip contains some solutions and their ramifications.

Convergence and Limitations

DC and transient solutions are completed by the simulator conducting an iterative process which terminates when the nonlinear branch currents converge to within a tolerance of 0.1 percent or 1pA, whichever is larger, and when the node voltages converge to within a tolerance of 0.1 percent or 1uV, whichever is greater. To improve convergence of DC and Transient Analyses, the user can do several things to help themselves. One also must understand the limitations of the analyses and the options to get correct and speedy results.

What is non-convergence? There are several types. No solution in the DC operating point. No solution in the DC step analysis. The timestep is too small in the transient analysis. The error tolerance is bi-conditional and depends on the accuracy error and the range error. These are determined by RELTOL (range error) and VNTOL (accuracy error) or ABSTOL (accuracy error). When all node voltages and all branch currents in the system equations agree with their previously computed value by xTOL, convergence occurs.

To improve convergence chances in any simulator, one can use several commands to help out. For a DC analysis, convergence can be helped using the .NODESET command. Changing the DC iteration limit, ITL1, to a higher value can help. Relaxing the convergence criteria by loosening RELTOL, ABSTOL and VNTOL will also improve convergence, but will reduce the accuracy by definition. To help out convergence in Transient Analyses, other help is necessary. The .IC statement will help similarly to the .NODESET command in the DC analysis case. The TRTOL option can be increased. This opens the area in which a valid solution CAN be found. Sometimes tightening the convergence criteria will help it converge.

There are limits to all analyses in simulation. It is important for the user to understand some of these limitations, so as not to be fooled by the simulation results. The simulation is only as good as the model for the circuit under consideration. Most parasitics are not included in all models. Parasitics also exist in metal traces along a PC card or IC surface, such as capacitance and resistance. This should not be ignored in analog design.

In AC analyses, the solution is only valid for that particular operating point at which the analysis was conducted. Transient analyses must have the tolerances tightened considerably in order to give accurate step responses.

For transistors, a number of limitations are evident. It is difficult to fit the models to the transistors’ characteristics in the various regions of operation. Worst case models are very difficult to determine because of the number of degrees of freedom found in the model. Parasitic devices have to be modeled separately by including the actual parasitic device in the schematic or netlist. Breakdown of the transistor is not simulated.

Circuits cannot contain a loop of voltage sources and/or inductors. Each node in the circuit must have a dc path to ground. Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes(which have two internal connections anyway).

For using Transmission Lines (the T element), only one propagating mode can be modeled with this element. To simulate all four nodes as distinct points in the actual circuit, then two modes may be excited and two elements are required. SPICE will use a transient time-step which does not exceed one-half the minimum transmission line delay. Therefore very short transmission lines(compared with the analysis time frame) will cause long run times.

If the simulator tells the user that "No solution in DC operating point" has occurred, this is catastrophic to the simulation. To solve this, the user needs to set the number of iterations to a much higher number. This is accomplished by setting ITL1. Try adding .NODESETs to your input deck. The user should verify ABSTOL, VNTOL and RELTOL. A final consideration is to verify the model and/or shrink is valid both nominally and at temperature.

The "No solution in DC step analysis" error is not too catastrophic, however. Again, many solution points are required for this analysis. The previous solution can be used as the initial "guess." This can be helped along by setting the number of iterations lower and using some predictor modifications to help out the N-R algorithm. The user can also set ITL2 to a higher number. This is the DC step iteration limit.

The disadvantage of reducing the iteration setting is that the simulation will take longer to run. More points for a given range require more solution points. The simulator is still doing a step analysis. DC sweeps calculate each step and cannot move back if the solution does not converge. This is why we must reduce the iteration points if step response changes are large. If the user is having problems with a DC step analysis, it is not recommended to set the step size to a small value. Instead, it should be replaced with a SLOW transient analysis.

What about the "Timestep too small in transient analysis" case? This occurs for a number of reasons. In the step analysis, many solution points are required. The previous solution may be used as the initial "guess." Non-convergence isn’t as catastrophic in this case. First, the user can set the number of iterations low. The timestep can be cut down in size. Some predictor modification can be added to help out the N-R algorithm. The ITL4 option can be raised. This is the transient iteration per timepoint setting. TRTOL can also be increased to a higher number. The user should verify the model at temperature and/or its shrink is valid.

By reducing the iterations in this analysis, we will again have a longer simulation time. However, the transient analysis CAN cut the timestep automatically if the solution is not found at the simulator’s selected time step. By adjusting the TRTOL option, the user opens up the valid solution space. One must be careful opening this option too much. Several valid solution points may exist in the space and the result indicated could be erroneous.

Some recommendations for making smoother transient analyses should be noted. Again, try using the TRTOL option between 1 and 100. For high gain circuits, set the maximum timestep to a small value. For example, .TRAN 1ns 200ns 0.0 0.05ns. For oscillators, set the maximum timestep to the value of 1/(2*f). For simulation of digital circuits, set the maximum timestep to 1/(2*f). This corresponds to half a period or clock frequency in time.

Again, caution should be noted when using these techniques to prevent erroneous results. The user should always set the maximum timestep to something equal or less than the print interval. For instance,

.TRAN .2ns 200ns 125ns

could result in an error. But, the following could easily correct the error:

.TRAN .2ns 200ns 125ns .2ns

Why is timestep control so important? The timestep determines the accuracy of the transient analysis. We use timestep control to calculate the current through the charge storage elements of the circuit. It controls the speed of simulation, the accuracy of the simulation and the ability to converge to a solution. So, if the number of iterations is greater than the threshold of solution, then decrease the timestep. The opposite is also true. If the number of iterations is less than the threshold of solution, then increase the timestep. Many iterations are needed for circuits with small time constants.

The TRTOL option is best used with op-amps and comparator circuits, due to their inherent high-gain nature and therefore large changing signal levels. It is also useful with high-speed digital gates and high-speed oscillators.

What do you do when a voltage node equals some unbelievable value, like 457V, when the highest source voltage is only 5V? This is the result of numeric integration oscillation. This can be remedied by changing the integration method from the default trapezoidal method to the Gear method. The trapezoidal method is the default because it is fast, but it is marginally stable. The Gear method is much slower, but very stable. The Gear number, MAXORD, as it is increased from 2 to 6, increases the simulation time and stability. The default is 2.

Another simple trick for fast changing nodes, such as the output of a digital inverter, is to add an "invisible capacitor." By simply adding a capacitor from the problem node to ground with a value of 10E-15F, it can be enough to help out the integration algorithm, but nowhere near enough to cause erroneous delays. Do not add capacitors everywhere, because this increases the size of the program at an alarming rate. The nodal matrices the program uses grows with each node and element added. Matrix manipulations can account for up to 75 percent of the simulation time. With 50 nodes, about 2500 elements will exist in matrices. With 100 nodes, the count increase to about 10000 elements!!!!

A final note on convergence. There is NO equation to guarantee your circuit will converge! If you follow the guidelines considered above, you will have a good chance of success. Please also note that not all nonconvergence results are due to problems with SPICE!!!! It sometimes indicates a true problem with the circuit under consideration. Check the circuit carefully.

Related discussions

Bookmark or share