Startup fields Spice debugging tool (Sandwork Design)

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LOS ALTOS, Calif. - October 30, 2001 - Sandwork Design Inc. is fielding what it calls the first third-party "transistor-level" debugging tool, named Spice Explorer. The offering includes a "lint" capability that finds problems in Spice netlists, and a waveform viewer with multiple display options.

The four-person startup, founded in May 2000, has been selling products since this spring, but has not yet made any public announcements. The private company is entirely self-funded.

"What we're trying to develop here is pretty much like [Novas Software's] Debussy in the Verilog world, except we're emphasizing transistor-level simulation," said Jack Yao, president of Sandwork. Spice Explorer works with virtually all commercial Spice and Spice-like simulation products, he said.

Yao was a key developer of ADM, an analog circuit simulation product developed by Anagram Inc. before that company was acquired by Avanti Corp. Yao, a former student of EDA luminary Andrew Yang, founded Sandwork after working at both Anagram and Avanti.

Transistor-level debugging tools today are scarce and inadequate, according to Yao. He said that some people are trying to use digital tools, like Debussy, for Spice simulation, while others are using "primitive" vendor-specific analog display tools. "None of the vendors have a good analog viewer with enough capacity and features for mixed-signal design," he said.

A key module of Spice Explorer is LintView, which can pinpoint problems using an interactive message browser. "It's not just syntax checking," said Yao. "We actually go into the circuit and find potential issues like floating blocks."

Topology checker
Spice Explorer takes HSpice format, which is supported by most commercial analog simulators, Yao said. HSpice has some strict rules with respect to passing parameter values, and LintView will watch for those, he noted. He said the lint capability will check for topology issues, such as gates that aren't connected to anything, and will flatten hierarchical netlists to check for connectivity problems.

Users can choose to suppress warnings for certain types of errors, but can't yet add their own rules, Yao said. He claimed that Sandwork has run internal tests in which a workstation with 2 Gbytes of RAM was able to check a 10-million-transistor netlist in as little as 5 to 10 minutes.

WaveView is Spice Explorer's simulation output viewer. It supports such options as logic timing diagrams, analog plots, histograms, Smith charts, sweep plots, polar charts and eye diagrams. "All of these are interactive, and you can zoom in and out and measure things," Yao said.

He noted that Sandwork has developed its own internal compressed format, called WDF, in order to reduce file size and loading time. Nassda Corp.'s HSIM simulator can output this format directly, he said. The company is working with other EDA vendors in hopes that they also will output WDF.

WaveView is integrated into Cadence Design System Inc.'s Analog Artist environment, Yao said, so that users can cross-probe between Cadence schematics and the simulation output display. In addition to HSpice format, Spice Explorer can read files output by Cadence's Spectre simulator.

Spice Explorer contains other modules as well. ChipView looks for design problems in physical layout plots that are extracted from Detailed Standard Parasitic Format netlists. DeckView displays the input Spice deck structure. GateView traces signal flows in the design.

SigView consolidates waveform data into a single hierarchical browser. CellView converts netlist definitions into graphical representations. NetView traverses the design hierarchy of flattened netlists. And FileView summarizes the input file structure in file trees.

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