MOUNTAIN VIEW, Calif. - May 7, 2001 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today extended its verification portfolio with the announcement of NanoSimâ¢ for memory and mixed-signal verification. NanoSim combines best-in-class circuit simulation technologies from TimeMillÂ® and PowerMillÂ® and offers tight integration with the industry-leading VCSâ¢ Verilog simulator to deliver high-speed, high-capacity verification of complex chip designs such as SoCs with analog, digital and memory sub-circuits on a single chip. NanoSim and VCS together address verification challenges at different levels of abstraction - RTL, gate and transistor - and enable mixed-signal SoC verification. NanoSim further enables this flow by supporting Verilog-A, the industry-standard analog behavioral modeling language.
"At Motorola, we are competitively challenged to deliver increasingly complex, compact SoC designs right-to-market in ever-shortening cycles," said Eytan Hartung, BaseBand functional manager of the Motorola Wireless Integration Technology Center, Motorola WITC. "The NanoSim interface to VCS helps us meet these challenges, offering extensive support for all VCS and NanoSim features, Verilog debugging, plus robust timing and power diagnostics that integrate seamlessly into our mixed-signal verification flow. We are pleased with the results from our first successful application and we are deploying this capability in the design flow for upcoming projects."
NanoSim offers a number of additional benefits to circuit designers that make it an ideal choice to meet some of the toughest transistor-level verification challenges. Based on Synopsys' proven circuit simulation technology, NanoSim handles multi-million transistor designs and allows designers to perform both power and timing analysis in a single simulation run, greatly streamlining the verification flow.
"We have been using TimeMill to verify functionality and timing performance of large custom circuit blocks," said David Nelson, circuit designer, Honeywell Solid State Electronic Center. "Using NanoSim I discovered a timing marginality problem that I had not seen before in my existing circuit."
NanoSim delivers very high capacity for memory verification, thanks to Synopsys' new Hierarchical Array Reduction (HAR) technology. HAR allows a user to efficiently simulate large memories made up of hundreds-of-millions of transistors using user-specified vectors.
NanoSim also seamlessly integrates with an existing design flow and shares the same commands, scripts, and libraries as PowerMill and TimeMill. This means that any designer familiar with PowerMill or TimeMill requires no additional expertise or training to run the tool, which makes NanoSim easy to use and adopt, and increases designer productivity.
"NanoSim leverages our best-in-class verification technologies," said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Group. "With the introduction of NanoSim, Synopsys is delivering the ability to perform both timing and power diagnostics in a single simulation run. With its advanced features including Hierarchical Array Reduction (HAR), Verilog-A support and VCS integration, NanoSim delivers a comprehensive solution that helps customers protect their verification suite investments, reuse their current design source, and save time and costs in training."
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