Synopsys announces NanoSim integration with the Cadence Analog Design environment (Synopsys)

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MOUNTAIN VIEW, Calif. - July 2, 2002 - Synopsys, Inc. (Nasdaq:SNPS) today announced the integration of Synopsys' NanoSim™ circuit simulator with the Cadence® Analog Design Environment using the Cadence Open Analog Simulation Socket (OASIS). This integration is a result of Synopsys collaboration with Motorola's Semiconductor Products Sector, completed through platinum membership in the Cadence Connections® Program. The combined solution enables companies like Motorola to verify large analog mixed-signal system-on-chip (SoC) designs, leveraging NanoSim's speed, capacity and accuracy directly from within the Analog Design Environment.

"Synopsys' NanoSim and the Cadence Analog Design Environment are critical pieces of our analog design and verification flow," said Jim Caravella, manager of Analog Design Kits and AMS Flows at Motorola's SPS. "We rely on NanoSim for transistor-level full-chip verification of our complex SoCs- and we use the Analog Artist Design Environment as the cockpit for analog, custom and mixed-signal design validation. Bringing the two together give our analog designers direct access to NanoSim from within the Analog Artist Design Environment, enabling our designers to quickly characterize and debug their analog/custom/AMS designs within a consistent and familiar environment."

The NanoSim fast-SPICE simulator delivers significant speed and capacity advantages over traditional SPICE simulators with SPICE-level accuracy. The comprehensive, built-in diagnostic functions of NanoSim enable users to perform a wide range of full-chip timing, functionality and power management tasks simultaneously. NanoSim offers a multi-level, mixed-signal verification solution through the Direct Kernel Integration with Synopsys' VCS Verilog simulator.

"Our collaboration with Motorola has resulted in an integrated solution that enables streamlined, precise analog mixed signal verification of world-class chips," said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test business unit. "The success of this joint project exemplifies Synopsys commitment to design partnerships that drive innovation and support our best-in-class design flow."

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