SAN JOSE, California - July 8, 2002 - Celestry Design Technologies, Inc., the leading provider of Silicon Accurate Sign-off technology for the semiconductor and electronics industry, announced today that it is introducing a universal model, AgeMOS, for accurate reliability modeling during deep-sub micron CMOS circuit simulation. In addition, Celestry is announcing tools and services that support model development and reliability modeling options for its transistor-level circuit simulators.
AgeMOS models enable the flexibility to incorporate new degradation mechanisms of transistor degradation into the circuit simulation. It is more accurate than previous generations of reliability models. They work with popular transistor-level circuit simulators, like Celestry's UltraSim, a multi-million transistor simulator.
"The AgeMOS model enhances our position as the leader in modeling and reliability analysis, said Randy Smith, Vice President of Marketing at Celestry. "The model's flexibility allows customers to use AgeMOS models in their 0.13 micron flows as well as in future very deep submicron flows." Smith also remarked, "We are currently working with several semiconductor manufacturers, who will support AgeMOS models in their cell-based flows."
Celestry's AgeMOS model offers reliability analysis for HCI (Hot-Carrier Injection) and NBTI (Negative Bias Temperature Instability) effects to improve performance and yield. The AgeMOS modeling methodology allows designers to select the best level of accuracy for their application, and use techniques to design more aggressively without overly pessimistic design guard bands.
The AgeMOS model is a universal model that works with any SPICE or SPICE-compatible simulator.
Celestry's AgeMOS model generation tools include RelPro+ for collecting stressed device data and BSIMPro+ for model parameter extraction. Celestry's circuit simulators that support AgeMOS models for block and full chip simulation are RelXpert and UltraSim, respectively.
Celestry and Reliability-HCI and NBTI
HCI degradation slows down circuit speeds, potentially causing circuit-operating failures. HCI arises as a result of the aggressive scaling of device geometries, most notably for short device channel lengths.
NBTI is a failure mechanism that degrades the dynamic range, distortion and matching of an analog circuit during high temperature operation, such as burn-in. NBTI degradation is a critical reliability issue for chip processes using ultra thin gate insulators, and can prevent a chip designer from relying on the expected performance of the process before NBTI stressing.
For more information on Celestry's reliability solutions, please read our technical brief.
Price and Availability
The AgeMOS option for Celestry's simulators starts at $30,000 (USD) and is available now. Celestry Labs also offers services for generating AgeMOS models.
Celestry is the leading provider of physical design products that enable integrated circuit designers to achieve optimal performance from semiconductor process technologies. The Company offers software and services to electronic and semiconductor companies involved with the design of chips that are used in networking, communication, multimedia and computing products.
Celestry Design Technologies, Inc. is headquartered at 2560 Junction Avenue, San Jose, CA 95134, USA. For more information visit www.celestry.com, email firstname.lastname@example.org or call 408-451-1210.