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A method for extraction and simulation of transient behavioral models of state transition of digital I/O buffers is introduced. This scheme increases the speed of chip interconnect simulations with large number of simultaneous switching devices, while maintaining good accuracy compared to corresponding transistor level models. This paper covers the derivation procedures of such transient state transition behavioral models from IBIS modeling data. A comparison of simulation results between these models and transistor level models (SPICE models) is also included.