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DynaCore - A timing sign-off solution for custom block and full chip path tracing analysis for SoC, with SPICE accuracy and built-in optimum vector generation.
DynaCore is a next-generation, timing analysis, and modeling tool for multi-million-transistor designs. Designers have the capability to time the entire design at the SPICE level, using either Circuit Semantics' built-in SPICE engine or an external commercial simulator, and then running Circuit Semantics' path tracing analysis. The DynaCore static timing analysis environment allows both custom and ASIC design flows to co-exist. DynaCore enables designers to quickly analyze timing bottlenecks, produce critical and sub-critical paths, slack analysis, and various types of timing models. In addition, Cadence's Pearl and Synopsys' PrimeTime are supported. Another key capability is incremental characterization, resulting in vastly decreased times for ECOs.