Mountain View, Calif. - November 10, 2002 - Apache Design Solutions, provider of Physical Design Integrity solutions for system-on-chip (SoC) designs, today announced the release of NSPICE, a new analog circuit simulator with several capabilities that have never before been offered in a fully HSPICE(TM) compatible simulator. These capabilities include:
NSPICE is targeted for system integrators and designers of chips, boards, connectors, and backplanes for the high-speed, multi-gigabit communications, networking, and graphics markets. NSPICE is also the simulation backplane for Tomahawk, the company's recently announced flagship product for SoC power network analysis and power integrity.
"NSPICE bridges the gap between chips and systems," said Andrew Yang, founder and CEO of Apache. "Until now, there has been no way to simulate critical high-speed interfaces -- from the chips, to package, to board, to backplane and back again. Now with NSPICE, they can simulate combined on-chip and system effects for a thorough, accurate analysis of very complex environments."
"Our flagship Virtex-IITM platform FPGAs demand simulation that accurately correlates the Rocket I/OTM serial transceiver behavior and performance with silicon," said Atul Ghia, Director of Product Development for the high-end FPGA group at Xilinx. "NSPICE enables us to directly use S-parameter models for modeling serial backplane, chip-to-chip and other topologies. In addition, NSPICE provides significant throughput and memory improvement, and completes simulations that other tools cannot support."
Mixed-domain simulation using actual S-parameters
With an increase in gigabit-per-second data rates on multi-port signals, the key issue that affects I/O design is the accurate modeling of system loading from the package, connector, and PCB traces, together with on-chip drivers and receivers. At high frequencies, S-parameter data is the most accurate form of broadband frequency-domain representation. Existing time-domain SPICE methods cannot take in S-parameters directly; the models must be manually fitted or translated into a lumped RLC approximation. This is a month-long process that may, at best, work in a narrow frequency range. Other simulators that do take in S-parameter directly suffer from serious limitations in capacity, and worse, may take longer to converge due to the internal fitting process. In addition, they are not fully HSPICE compatible.
NSPICE enables fast and accurate mixed-domain simulation of multi-gigabit serial I/Os by taking in S-parameters directly from the board, and simulating them with large on-chip circuits such as high-speed drivers and receivers. By using NSPICE, designers can directly simulate circuits containing hundreds of thousands of transistors and parasitics combining on-chip and off-chip configurations (such as a transmitter + package S-parameters + backplane S-parameters + receiver) that are commonly used in multi-gigabit transceivers, Serdes drivers and gigabit Ethernet applications. NSPICE provides the most accurate simulation of S-parameter data; with results confirmed by silicon measurement down to picosecond accuracy across a broad frequency range.
Signal integrity and nanometer checks for stress, leakage and IR drop
NSPICE considers signal integrity issues during simulation, such as transmission loss, cross-coupling, timing jitter and skew, and IR drop, thereby eliminating the dependency on multiple tools and enabling faster convergence. Emerging nanometer effects such as leakage current, device stress, and headroom are also accounted for. "We require a reliable method to safeguard each MOSFET from transient glitches causing device stress in circuits using multiple supply voltages," said Leechung Yiu, vice president of engineering at Marvell Semiconductor. "NSPICE allows us to quickly pinpoint when and where these dangerous nanometer effects can impact our circuits."
Improved performance, convergence and HSPICE compatibility
NSPICE is written in C++ from scratch and employs hierarchical algorithms offering improved performance, memory efficiency, and better convergence using advanced matrix solver technology. The product is fully compatible with HSPICE, and SPICE models and netlists. In addition, it supports fast and automatic "eye" diagram generation and viewing.
"Apache's development of NSPICE signals increased market demand for a next-generation SPICE that addresses larger device counts and faster circuits while improving accuracy," said Keith Mueller, Apache vice president of sales and marketing. "And with inductance gaining importance in package, clock, and power mesh structures, NSPICE constitutes a critical simulation component of Apache's physical design integrity solutions for power, timing and system I/O in large SoCs."