Silvaco rolls out SmartSpice-RF and inductance extractor (SIlvaco)

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Santa Clara - June 1, 2004 - Silvaco International today announced the release of SmartSpice-RF Harmonic Balance-Based Simulator and QUEST High Frequency Parasitic Extractor. SmartSpice-RF provides a complete set of steady-state analyses to design GHz range RF wireless application ICs. QUEST calculates 3D frequency dependent inductance, resistance, capacitance and capacitive loss for any multi-port network for RF SPICE analysis.

“RF IC design engineers require harmonic balance circuit simulation and an effective noise solution to prove their designs,” said Ken Brock, vice president of marketing at Silvaco. “SmartSpice-RF accurately and efficiently simulates noise, gain compression, harmonic distortion, oscillator phase noise, and intermodulation products in non-linear circuits using SPICE netlists.”

SmartSpice-RF harmonic balance simulator provides frequency-domain steady-state large signal analysis of non-linear circuits driven with multi-tone sources. It performs complete set of periodic and quasi-periodic steady state analyses for large-signal and small-signal applications—each with full parametric sweep and Monte Carlo control parameters. Applications include amplifiers, mixers, multipliers, oscillators, VCOs, AGCs, PLLs, muxs, demuxs, clocks, CDRs and other RF circuits.

Accurate Wireless Measurements and Optimizer
SmartSpice-RF measures spectral regrowth, ACPR, NPR simulations of amplifiers/mixers, I/Q modulator simulations, characterization of the transmission link quality of communications systems, and other key wireless measurements. It includes a powerful parameter optimizer for gain, matching networks, IP3, and power dissipation for new circuit design or process migration.

QUEST High Frequency Parasitic Extractor
QUEST calculates 3D frequency dependent inductance, resistance, capacitance and capacitive loss for any multi-port network for RF SPICE analysis. It creates frequency dependent W-element transmission lines, multi-port S-parameters, and spiral inductor standard SPICE models directly from GDSII layouts using an interactive GUI interface.

Complete RF Design Environment
SmartSpice-RF leverages all SmartSpice models for large-signal, small-signal, noise, and parameter output. It is integrated with Silvaco’s complete, PDK supported, mixed-signal/RF physical design flow consisting of Gateway Schematic Editor, SmartSpice Circuit Simulator, Expert Layout Editor, Guardian DRC/LVS/LPE and HIPEX Full-Chip Parasitic Extraction. It also can be used within other popular EDA flows.

Pricing and Availability
SmartSpice-RF and Quest are available now on Linux, Windows, and Solaris. Perpetual, time-based, and site licenses are available for workgroup configurations of these products. List price for SmartSpice-RF starts at $60,000 for a time-based license. For further information on these products, please contact

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