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Arana platform automates the process of behavioral model creation, generation, optimization, and validation for analog, custom digital, memory and mixed-signal integrated circuits. It features Arana Top-Down Designer, Arana Bottom-Up Designer, Arana Model Optimizer, and Arana Model Validator. Arana Top-Down Designer supports behavioral model creation from specification or from templates, as well as automated calibration of model parameters against the transistor response and/or measurement data. Arana Bottom-Up Designer allows a circuit designer to automatically generate silicon-faithful parametric behavioral models-ccounting for process, voltage, temperature, and loading variations-or functional verification. Both Arana Bottom-Up Designer and Top-Down Designer support hierarchical modeling and automated generation of formal analog assertions and model test benches. Arana Model Optimizer and Model Validator optimize and validate behavioral models against transistor level responses and characterization and/or measurement data.
Arana has been tested by leading semiconductor companies on over 40 pre-layout and post-layout production circuits including operational amplifiers, comparators, bias generators, switches, charge pumps, analog to digital converters, digital to analog converters, source drivers, phase locked loops, delay locked loops, dc-dc converters, low-voltage differential signaling (LVDS), and Serializer/Deserilizer (SerDes).
Arana generated models accelerate SPICE simulation by 100 to 1000 times for complex mixed-signal circuits. It enables mixed-signal full-chip design verification and functional sign off, architecture exploration, IP reuse, and test development.