Solido Design Automation, a leading developer of software for reducing variation risk in nanometer designs at the transistor level, has opened up its Variation Designer platform for integration into third party simulators and design environments. Variation Designer, introduced to the market in January 2009, is the first truly scalable and extensible solution specifically developed to address variation challenges at the transistor level.
Along with Solidos PVT (process, voltage, temperature) Corner, Statistical and Proximity applications packages, Variation Designer can be deployed for transistor level design to account for global, local, environmental and proximity related variation effects. Using these solutions, customers are able to achieve better designs with reduced variation risk in less time. Customers have been able to achieve designs with 20-100% better area, power, performance, yield and a reduction in variation design time of over 50%.
Variation Designer is used across the transistor level design cycle from PVT corner simulations to statistical analysis to determine mismatch effects or yield. The platform is also useful for post-layout verification and, if required, for silicon debug. Intuitive to learn and easy to use, this interactive tool puts the designer in control. Variation Designer provides a systematic and consistent variation design flow for various transistor level design types (analog/RF, IO, memory or standard cell digital) that can be integrated with various simulator and design environments, providing a consistent interface to designers irrespective of their specific tool environments.
Variation Designer has been deployed for various flows such as Cadence® Virtuoso® Analog Design Environment (ADE) with Spectre Circuit Simulator, Virtuoso ADE with Synopsys HSPICE® Circuit Simulator, and HSPICE netlist. Designers use a wide array of flows comprised of different simulators and environments that depend on design type or simulation requirements. Having seen a strong desire by customers to integrate with their specific tool preferences, Solido has opened up their platform for integration by third-party simulator and design environment vendors.
As we have deployed Variation Designer at customer sites we have observed that designers greatly appreciate a consistent interface for their transistor level designs, said Amit Gupta, president and CEO of Solido Design Automation. Integration with Variation Designer will enable our partners to provide a consistent interface to help their customers reduce variation design risk and also to benefit as additional applications are launched to solve new and existing variation problems.
Solido Design Automation, Inc. (Solido) provides software for reducing variation risk in nanometer designs at the transistor level. Solidos Variation Designer and application packages are used by analog/RF, IO, memory and standard cell digital designers to achieve better designs with reduced variation risk in less time. The privately held company is venture capital funded and has offices in the U.S.A., Canada, Japan and Europe. For further information, visit www.solidodesign.com or call 306-382-4100.